The invention concerns a fractional-N frequency synthesizer for generating high frequency signal at frequency that may be a non-integer multiple of the reference frequency. If it is necessary, this high frequency signal could also be modulated simultaneously to carry information.
Fractional-N frequency synthesizer is under intensive research for many years. It permits the synthesizer to use a reference signal with higher frequency to improve noise performance and lock-in speed. The main trade off is the introduction of the fractional spurs. Many techniques are invented to reduce the spurs level. One of the successful approaches is the Delta-Sigma noise shaping technique, which could significantly reduce the spurs level and bring the possibility to digitally add the phase or frequency modulation to the synthesized signal. However, for some application the improvement is not enough and the fractional spurs may still be a problem. Besides, significant portion of analog circuit is still needed which is also a limiting factor on the performance and the integration level.
The main analog circuit of a conventional synthesizer is the phase detector. The DSFD (Delta-Sigma Frequency Discriminator)[R. Douglas Beards and Miles A. Copeland, “An Oversampling Delta-Sigma Frequency Discriminator”, IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, Vol. 41, No. 1, Jan. 1994, pp.26-32] could be used to replace the phase detector in Fraction-N frequency synthesizers [U.S. Pat. No. 5,781,044] and modulators [W. T. Bax and M. A. Copeland, “A GMSK Modulator Using a Frequency Discriminator-Based Synthesizer”, IEEE Journal of Solid-State Circuits, Vol. 36, No. 8, Aug. 2001, pp.1218-1227]. The DSFD has the function of a frequency discriminator with the unique feature that the detected signal is in digital format representing the Delta-Sigma quantization to the fractional frequency of the input signal. Thus the synthesizer could be formed by using digital signal processing to generate the control signal for the VCO (Voltage Controlled Oscillator), which may be more precise and flexible. So from functional aspect it is a device that digitally quantizes the phase or frequency difference to be measured. There are also other patented inventions with the similar functions (such as U.S. Pat. No. 6,107,890 etc.). This type of the detection is advantageous in the application where the digital signal processing is preferred, but most of the previous proposed structures have limitations on some of the performances such as resolution, accuracy or response time so that their application is also limited.
The first order DSFD shown in FIG. 1 is very attractive since it is formed with only a DMD (dual modulus frequency divider) (1) and a D flip-flop (2). However, the above mentioned invention and applications to use the DSFD always extract the error information from the outputted digital signal directly by calculating the difference between the average value of that signal and the desired fractional number for the signal frequency to be synthesized and then suppressing the fractional spurs by decimation and loop filtering. Mathematically this is correct according to the principal of Delta-Sigma modulation. But to use the first order DSFD in this way will result in very high fractional spurs since it only performs first order Delta-Sigma modulation. This is why the second or higher order DSFD is suggested and used in the reported implementations. The problem is that the structure of the higher order DSFD is much complicated and analog phase detector is used in the structure. So although the resulted synthesizer does contain more digital signal processing, its accuracy and noise performance are obviously questionable due to that more and complicated analog circuit is also used.
There are generally two ways for fractional-N synthesizers to reduce the fractional-N spurs. Besides the higher order Delta-Sigma noise shaping method, the more traditional way is to add the analog compensation signal to the synthesizer with the first order Delta-Sigma modulation. The compensation is possible because the fractional phase jitter has its own evolution rules. It is well known that the performance of such synthesizer could be very good, but is very sensitive to the precision of the analog circuit, which is subject to variations as a function of time and temperature.
It will be worthwhile to investigate whether it is possible to remove the fractional spurs generated by the first order DSFD using also the evolution rules of the fractional phase jitter. If this is possible and it is also performed by the pure digital signal processing that has no problem of analog mismatch, then the resulted synthesizer could be quite ideal: low fractional spurs and almost pure digital implementation. This is exactly what will be disclosed by this invention.